The present invention relates generally to a semiconductor memory, and more specifically to a nonvolatile memory cell for prevention form second bit effect.
Among semiconductor memories, the nonvolatile memory, especially the electrically erasable programmable read only memory (EEPROM), is particularly useful due to its advantage of retaining information even power is turned off, and its application also becomes more popular. Similar to other semiconductor memories, the nonvolatile memory is developed toward scale down to increase the memory capacity. New and improved memory cell structures and better programming mechanisms are proposed to improve the performance of nonvolatile memory. For example, a perpendicularly accelerated channel injection CMOS (PACMOS) is disclosed by M. Kamiya, Y. Kojima, Y. Kato, K. Tanada and Y. Hayashi, xe2x80x9cEPROM cell with high gate injection efficiencyxe2x80x9d, IEDM Tech. Dig., 1982, pp 741-744, with a structure to enhance the channel injection to increase the injection efficiency. On the other hand, to increase the density of memory circuit and lengthen the electrical charge retention time, an oxide-nitride-oxide (ONO) structure has been used to replace conventional stack memory cell, which has the benefit of easy process and high density, for example, referring to T. Y. Chan, K. K. Young and Chenming Hu, xe2x80x9cA true single-transistor oxide-nitride-oxide EEPROM devicexe2x80x9d, IEEE Electron Device Lett., vol. EDL-8, pp 93-95, 1987 and U.S. Pat. No. 5,168,334 issued to Mitchell et al. By storing two bits in a single memory cell the memory capacity can be doubled, for example, referring to U.S. Pat. Nos. 5,768,192, 5,963,465 and 6,011,725 issued to Eitan. However, new problems are introduced. Two bits stored in a single memory cell may cause interactions between each other of them, especially for the electric field from the stored charge of one bit to influence the other bit when the latter is manipulated. Or when one bit is manipulated, the voltage applied has effect on the other bit. One of the known undesired situation is called second bit effect, by which the threshold voltage of second bit is lowered due to the source side injection occurred in the transistor when writing the second bit and the electron packet of the first bit spreads to result in over writing. The adverse effect has a more serious impact on the shrunk devices. Therefore, it is desired a nonvolatile memory cell for prevention from second bit effect.
One object of the present invention is to provide a nonvolatile memory cell to inhibit the second bit effect when writing data into the memory cell.
Another object of the present invention is to provide a double bit nonvolatile memory cell to double the memory capacity in single memory cell.
Still another object of the present invention is to provide a highly integratable nonvolatile memory cell to produce high density semiconductor memory.
Yet another object of the present invention is to provide a nonvolatile memory cell with ONO programmable layer to obtain the benefit of easy process and high density as for stack memory cell.
According to the present invention, a nonvolatile memory cell for prevention from second bit effect comprises a channel on a semiconductor substrate and a pair of source/drain regions at opposite sides of the channel. Above the channel is arranged a programmable layer and a gate conductor over the programmable layer. The programmable layer has a first and second boundary between the programmable layer and the source and drain regions, respectively, and a maximum width larger than the widths of the first and second boundary to inhibit the second bit effect occurred within the nonvolatile memory cell.
The programmable layer comprises a trapping dielectric layer inserted between two insulator layers. The trapping dielectric comprises a nitride or an oxide with buried poly-silicon islands, such that the regions at each side of the trapping dielectric layer close to the source and drain regions may provide for storing a bit, respectively.
In a preferred embodiment, the memory cell according to the present invention has a hexagonal gate.